An electrically erasable, non-volatile, programmable memory device (EEPROM) includes a floating gate between a control gate and the semiconductor substrate. A tunnel oxide as well as a gate oxide is provided between the floating gate and the substrate and an insulating layer is provided between the two gates. To program an EEPROM cell, potential is placed on the floating gate by the capacitive coupling from the control gate to the floating gate and the coupling from the floating gate to a diffusion in the substrate beneath the floating gate. When these effects are designed correctly, the correct amount of charge is stored on the floating gate and changes the threshold of the device. This is then sensed in the support circuitry and recognized as a "1" or "0" depending on how it is programmed.
Heretofore, EEPROMs were applied, most frequently, to applications in which high density was desirable. In order to achieve this, the cell size was minimized for maximum memory packaging density. One convenient way to reduce the cell size is to use a high program voltage, allowing the size of the capacitor between the control gate and the floating gate to be small. The tunnel oxide current equation dictates an absolute value of voltage required to pass tunnel current through it for a given tunnel oxide thickness. To obtain this voltage on the floating gate, the control gate voltage has to be increased when the capacitive ratio decreases.
The voltage on the floating gate during programming is determined by the voltage on the control gate and the ratio of the control gate to floating gate capacitance divided by the floating gate to substrate capacitance. As the capacitive ratio is increased, the voltage required on the control gate to attain a given potential on the floating gate is not as great. The capacitive ratio is primarily affected by the layout of the cell, i.e., a larger cell size will typically have a larger capacitive ratio.
It is desirable to combine EEPROMs with CMOS logic circuits. When high density is desired, the EEPROMs must be designed with relatively deep source and drain junction and thick field oxides to accommodate the high voltage programming. Attempts to integrate the high density EEPROM with CMOS logic circuitry, which is typically low voltage (typically about 5 volts or less) circuitry, necessitates that the entire device be dominated in some key respects by the EEPROM high voltage circuitry. These requirements tend to degrade the performance and reliability of the high performance, low voltage logic which typically has shallow source and drain junctions and thinner oxides. The deeper junctions used in the EEPROMs require that the channel length of the CMOS logic be wider to avoid short channel effects, resulting in slower logic devices. The thick field oxide of the EEPROMs increases the lateral encroachment "bird's beak" in the CMOS logic and thus a greater limitation is present in the minimum pitch of diffusion regions. Another longer range result of this is the limited shrinkability of the device and process with a high density/high voltage EEPROM.
At present, when forming a CMOS logic circuit with EEPROMs in a stacked poly FLOTOX technology, i.e., polysilicon gates and a thin insulator for electron tunneling, compromises are required in order to insure that one of the polysilicon layers of the EEPROM can be shared with the logic device. This is usually done by one of two ways. One method is to first define the floating gate of the EEPROM. A high temperature dielectric oxide is then grown which also serves as the gate oxide of the CMOS devices. Then the second polysilicon layer is deposited and defined to form the gates of the CMOS devices and the control gate of the EEPROM. Thus, the control gate of the EEPROM is shared with the CMOS device gates. In this method the high temperature dielectric oxide tends to degrade the characteristics of the tunnel oxide of the EEPROM. This high temperature shifts the implants in the CMOS device and thus creates a shift in the electrical characteristics from the CMOS process which would not occur without the EEPROM processing. Also, a silicon dioxide dielectric along between the floating gate and the control gate of the EEPROM is not easily made a reliable dielectric.
The second method is to grow the gate oxide and then mask and etch the windows for the tunnel oxide. A pre-tunnel clean step then follows. The tunnel oxide is then grown followed by pre-polysilicon deposition clean and polysilicon deposition. The first polysilicon layer is shared between the CMOS devices and the floating gate of the EEPROM. In this method the steps required between the gate oxidation and polysilicon deposition degrade the gate oxide and thus the performance of the CMOS circuit. The gate oxide is degraded by placing photoresist on it for the tunnel mask, the pre-tunnel oxide clean, and the tunnel oxidation itself. These steps may introduce contaminants into the gate oxide and will certainly alter the thickness of it during the tunnel oxidation.
Therefore, it is desirable to have a high reliable CMOS logic circuit in which an EEPROM can be inserted using the standard method for making the CMOS circuit and with negligible impact on both the CMOS circuit and the EEPROM.